ELECTRICAL INTERCONNECT AND MICROFLUIDIC COOLING WITHIN 3D ICs AND SILICON INTERPOSER

Heat dissipation is a significant challenge for threedimensional integrated circuits (3D IC) due to the lack of heat removal paths and increased power density. In this paper, a 3D IC system with an embedded microfluidic cooling heat sink (MFHS) is presented. In the proposed 3D IC system, high power tiers contain embedded MFHS and high-aspect ratio (23:1) through-silicon-vias (TSVs) routed through the integrated MFHS. In addition, each tier has dedicated solderbased microfluidic chip I/Os. Microfluidic cooling experiments of staggered micropin-fins with embedded TSVs are presented for the first time. Moreover, the lateral thermal gradient across a chip is analyzed with segmented heaters. INTRODUCTION Three-dimensional IC (3D IC) technology has been extensively explored in recent years. By significantly shortening the interconnect length as well as enabling heterogeneous integration of logic, memory, MEMS, and optoelectronics [1], 3D ICs reduce system power, system footprint and improve performance. A key challenge for high-performance 3D applications is heat removal. The reason is that both the power density of a 3D stack and the thermal resistance of the dice within the stack increase as the number of tiers increases. The latter is due to the fact that the inner dice do not have direct access to a heat sink (Fig. 1 (a)). Thus, innovative interlayer microfluidic cooling has been proposed for 3D ICs to overcome this challenge [3][4]. Due to the advancements in microfabrication, more ‘complex’ microstructures for improved heat sink performance have been fabricated and may outshine the performance of plain microchannels proposed in [3]. Examples of more complex microfluidic heat sink structures include enhanced microchannels [5], inline micropin-fins [6][7], staggered micropin-fins [8], and pearl chain [6] etc. Prior work in interlayer microfluidic cooling has focused on pumping a coolant into a stack through a single inlet, as shown in Fig. 1 (b) [6]. The authors demonstrated heat removal of 200 W and 400 W in a 2-tier stack and 4-tier stack, respectively in [9][10]. With this approach, it is not possible to control or tailor the flow rate in each tier. However, in a realistic 3D stack, especially in a heterogeneous stack, the power dissipation in each tier may be different (workload dependent). Thus, one needs the capability to control the coolant flow rate in each tier independently. Even more, there is likely a need to deliver the coolant to specific locations within a tier. To address this need, wafer-level batch fabricated solder microfluidic chip I/Os and fine pitch electrical microbump I/Os have been recently demonstrated [12]. Due to the integration of the microfluidic heat sink (MFHS), the chip thickness may become a few hundred micrometers, which presents great challenges to through-silicon-via (TSV) fabrication and electrical performance. Given the thickness of silicon dice with embedded microfluidic cooling, high-aspect ratio TSVs become critical in such 3D ICs and are explored in this paper. Proceedings of the ASME 2014 12th International Conference on Nanochannels, Microchannels, and Minichannels ICNMM2014 August 3-7, 2014, Chicago, Illinois, USA